1. Field of the Invention
The present invention relates to semiconductor device and method for manufacturing the same, and in particular to an improved semiconductor device and method for manufacturing the same wherein one side of a source and drain region and a portion of a channel region are disposed on a buried oxide layer formed on a semiconductor substrate and the side of the source and drain region and another portion of the channel region are disposed on a Si epitaxial layer formed on a semiconductor substrate to reduce a junction leakage current and junction capacitance and suppress a short channel effect thereby improving characteristics of the semiconductor device.
2. Description of the Related Art
FIGS. 1 and 2 are a layout illustrating a conventional semiconductor device, and a cross-sectional view of the conventional semiconductor device taken along the line I-I′ and II-II′ of FIG. 1, respectively.
Referring to FIGS. 1 and 2, the semiconductor device in accordance with the conventional art comprises a semiconductor substrate 10 having an active region defined by a device isolation film 25, and a buried oxide film 50 is disposed on a surface of the semiconductor substrate 10. A Si epitaxial layer 20 is disposed on the buried oxide film 50, and a channel region (not shown) and an LDD region 40 are disposed in the Si epitaxial layer 20. A gate structure, which comprises a stacked structure of a gate insulating film 30a, a gate electrode 35a and a hard mask film pattern 37a, is disposed on the channel region. A gate spacer 45 is disposed on a side of the gate structure, and a source/drain region 55 is disposed in the active region at both sides of the gate spacer 45.
FIGS. 3A through 3F are cross-sectional views illustrating a method for manufacturing the conventional semiconductor device shown in FIG. 2 taken along the line I-I′ and II-II′ of FIG. 1.
Referring to FIG. 3A, a SiGe epitaxial layer 15 and a Si epitaxial layer 20 are sequentially stacked on a semiconductor substrate 10. Thereafter, a device isolation film 25 defining an active region is formed on the semiconductor substrate 10.
Referring to FIG. 3B, an impurity is implanted into the Si epitaxial layer 20 to form a channel region (not shown). Thereafter, a gate insulating film 30, a gate conductive layer 35 and a hard mask insulating film 37 are sequentially formed on the entire surface.
Referring to FIG. 3C, the hard mask insulating film 37, the gate conductive layer 35 and the gate insulating film 30 are patterned to form a gate structure including a stacked structure of a hard mask insulating film pattern 37a, a gate electrode 35a and a gate insulating film pattern 30a. Thereafter, an impurity is implanted into the Si epitaxial layer 20 at both sides of the gate structure to form an LDD region 40.
Referring to FIG. 3D, a sidewall spacer 45 is formed on a side of the gate structure. Thereafter, a portion of the Si epitaxial layer 20, a portion of the SiGe epitaxial layer 15 and a predetermined thickness of the semiconductor substrate 10 at both sides of the sidewall spacer 45 are removed by etching to expose a side of the LDD region 40 and the SiGe epitaxial layer 15 and a side and a surface of the semiconductor substrate 10.
Referring to FIG. 3E, the SiGe epitaxial layer 15 below the gate electrode 35a are removed by an wet etching process to form a space under the Si epitaxial layer 20, i.e. under the LDD region 40 and the channel region.
Referring to FIG. 3F, an oxide film is formed in the space formed below the gate electrode 35a by removing the SiGe epitaxial layer 15 and the surfaces of the exposed portions of the Si epitaxial layer 20 and the semiconductor substrate 10. The oxide film is then etched to form a buried oxide film 50 filling the space below the gate electrode 35a. 
Referring to FIG. 3G, a silicon layer 55 is grown on the active region where the Si epitaxial layer 20, the SiGe epitaxial layer 15 and the predetermined thickness of the semiconductor substrate 10 were removed, and then subjected to an impurity implant process to form a source/drain region in the silicon layer 55.
As described above, in accordance with the conventional semiconductor device and method for manufacturing the same, the semiconductor substrate and the channel region is electrically isolated since the entire channel region under the gate electrode is formed on the buried oxide film, whereby the voltage applied to the gate electrode is only partially applied to the semiconductor substrate. Therefore, when the thickness of the Si epitaxial layer is reduced to suppress a short channel effect, a threshold voltage is also reduced since the threshold voltage is determined by the doping concentration of the channel region and the thickness of the Si epitaxial layer. Moreover, the source/drain region is electrically connected to the semiconductor substrate resulting in increase in junction leakage current and junction capacitance of the source/drain region.